1. Field of the Invention
The present invention relates to a self-synchronous FIFO memory device, and a system with an interface for data transfer using the same, and more particularly, to a scheme for controlling data input/output to/from an FIFO memory device.
2. Description of the Background Art
A logic circuit performing a pipelined data processing in synchronization with a clock is usually configured as a logic circuit LSI. Such a logic circuit LSI has attained higher speed and smaller size, year after year. That is, an interconnection length is made larger, and an interval between the interconnections is made smaller. Accordingly, a series resistance in the interconnection and a parallel capacity between the interconnections become larger. Because of this, delay of a signal and waveform rounding have been more significant. An effect thereof, however, considerably varies depending on the interconnection length. Therefore, it is difficult to have a uniform interconnection length toward all flip-flops arranged on an overall chip in a random fashion, as well as to distribute an in-phase single clock.
In order to avoid the problem, for example, it is necessary to generate a clock tree in which a buffer is arranged in a multi-stage tree structure, so as to achieve equal delay on the overall chip, which will increase the cost. Therefore, a logic circuit locally synchronizing adjacent pipeline registers and having a self-synchronous pipeline that does not require the in-phase single clock, has been discussed.
In the self-synchronous pipeline, when data transfer is temporarily forced to be stopped at an output end of the pipeline, for example, due to the fact that a subsequent device is in a state in which it cannot receive output data from the pipeline, the data transfer is forcibly stopped in a chained manner toward an input end of the pipeline. Then, it will be necessary to wait at the output end of the pipeline until the data transfer is permitted again. During this process, by “squeezing” the data in the pipeline normally flowing with a certain interval, an autonomous buffering capability is attained. If the buffering capability is overcome, however, a state in which the data cannot temporarily be received at the input end of the pipeline will be caused.
In such a case, it is desirable to reinforce the buffering capability by inserting the FIFO memory device in the pipeline. In addition, if the data is transferred between two different systems having a self-synchronous pipeline configuration, and particularly if a data transfer rate is different therebetween, it is desirable to insert the FIFO memory device between the two systems, to transfer data in response to an independent write/read request, so that one system writes data in the FIFO memory device while the other system reads the data from the same, for example.
FIG. 13 shows an example of an FIFO memory device utilizing an autonomous buffering capability of the self-synchronous pipeline, as a conventional art. In FIG. 13, the FIFO memory device is configured with pipeline registers 81, 82, 83 constituting a pipeline, and self-synchronous transfer control circuits 84, 85, 86 supplying a clock to a pipeline register while establishing handshaking with one another. Hereinafter, the self-synchronous transfer control circuit is denoted as a C element, and a set of one C element and one pipeline register operating with the clock supplied by the C element is denoted as a self-synchronous data transmission path.
Next, FIG. 14 shows an example of the inside of C elements 84, 85, 86 in FIG. 13. In FIG. 14, the C element consists of: a CI signal terminal 91 receiving a transfer request signal (SEND signal) from a preceding stage; an RO signal terminal 92 returning an acknowledge signal (ACK signal) indicating reception of the transfer request from CI signal terminal 91 to the preceding stage; a CP signal terminal 93 sending a clock pulse to the pipeline register in response to the transfer request from the CI signal terminal 91; a CO signal terminal 94 transmitting the transfer request from the preceding stage to a next stage; an RI signal terminal 95 to which the acknowledge signal indicating reception by the next stage of the transfer request from a CO output terminal is returned; a flip-flop 96 holding a transfer request reception state; an NAND gate 97 synchronizing flip-flops 96, 98; and flip-flop 98 holding a transfer request state to the next stage.
FIG. 15 is a timing chart showing an operation of the C element. When an “L” level signal is input to a pulse input terminal CI, that is, when the data transfer is requested from the preceding stage, flip-flop 96 is set, and an “H” level signal is output from an output node thereof. Then, the “L” level signal is output from a transfer permission output terminal RO, and further data transfer is prohibited. Hereinafter, signal terminals 91-95 refer to a pulse input terminal CI, a transfer permission output terminal RO, pulse output terminals CP, CO, and a transfer permission input RI terminal, respectively. These terminals are also simply denoted as CI (ci), RO (ro), CP (cp), CO (co) and RI (ri) terminals respectively.
After a certain time has passed, the “H” level signal is input to pulse input terminal CI, and setting of the data from the preceding stage to the C element is completed. When this state is established, when the “H” level signal is being input from transfer permission input terminal RI (that is, data transfer is permitted from the subsequent stage), and when pulse output terminal CO outputs the “H” level signal and data is not being transferred to the subsequent stage, NAND gate 97 is activated, and outputs the “L” level signal.
As a result, flip-flop 96 is reset and flip-flop 98 is set. Accordingly, the “H” level signal is output from pulse output terminal CP to the pipeline register, and the SEND signal of “L” level is output from pulse output terminal CO to the subsequent stage. That is, data transfer is requested to the subsequent stage. The C element in the subsequent stage that has received the SEND signal of “L” level sends the ACK signal of “L” level indicating prohibition so that further data is not transferred to the C element in the preceding stage. The C element in the preceding stage receives the ACK signal of “L” level input from transfer permission input terminal RI, and accordingly, flip-flop 98 is set. Consequently, the “L” level signal is output from pulse output terminal CP to the pipeline register, and the SEND signal of “H” level is output from pulse output terminal CO to the subsequent stage. Then, data transfer is terminated.
Transfer request signal (SEND signal) is input to C element 84 in the first stage of the pipeline in FIG. 13, and process data D is input to pipeline register 81 also in the first stage. Thus, flip-flop 96 within C element 84 holding the transfer request reception state is set, and an acknowledge signal ACK is returned from C element 85. Then, CI terminal of C element 84 returns to “H” level, and NAND gate 97 within C element 84 outputs “L” level. In addition, flip-flop 98 within C element 84 holding the transfer request to the next stage is set, and flip-flop 96 is cleared.
When a clock CP to pipeline register 81 of C element 84 attains “H” level, input data D is latched in pipeline register 81 for output to a node Q. In addition, a transfer request signal to the next stage is output to the CO terminal of C element 84. The signal is input to C element 85 constituting the second stage of the pipeline in FIG. 13. When C element 85 performs an operation similar to C element 84, data Q output from pipeline register 81 is latched in pipeline register 82 in the second stage, for output to node Q. C element 86 also operates in a manner similar to C elements 84, 85. That is, data output from pipeline register 82 in the second stage is latched in pipeline register 83 in the third stage, for output to output data terminal Q.
FIG. 16 shows another example of the self-synchronous FIFO memory device (FIFO) as the conventional art. This example shows a configuration in which n self-synchronous data transmission paths (a set of the C element and the pipeline register serving as a pair of the former) in FIG. 13 are connected in series. With reference to a timing chart shown in FIG. 17, an operation in a procedure for inputting (writing) n data, and outputting (reading) the n data after the FIFO attains a full state in the circuit shown in FIG. 16 will be described.
First, a procedure for inputting n data successively from an FIFO empty state will be described. When first data DATA1 is input from a terminal D with an “L” pulse signal input 12-1 (a write clock) from CI terminal, a C element 114 establishes handshaking with a C element 115 in the subsequent stage, as described in FIG. 15, and transfers first input data DATA1 to a pipeline register 112 in the second stage. Here, a pulse signal 12-2 indicating that transfer of DATA1 to the data transmission path in the subsequent stage has been normally completed is output from terminal.
More specifically, fall from “H” level to “L” level of the RO terminal indicates reception of the input data from the preceding stage, while rise from “L” level to “H” level indicates completion of a transfer operation of the received data to the subsequent stage.
C element 115 in the data transmission path in the second stage operates in a similar manner, and DATA1 is transferred to a pipeline register in the third stage. A C element in a following stage also operates in a similar manner, and DATA1 is transferred as far as a data transmission path in the nth stage. The C element in the nth stage also performs a normal transfer operation. That is, DATA1 is latched in a pipeline register 113 in the nth stage, an “L” level signal 12-3 is output from CO terminal, and DATA1 is output from data output terminal Q.
Further, a state in which CO terminal outputs the “L” signal indicates that data to be read is present (a read data ready state). In such a state, when an “L” level pulse signal (read clock) is input from RI terminal, CO terminal rises to “H” level, and an operation for reading DATA1 is completed. Here, however, the input signal of RI terminal is fixed to “H” level. That is, a state in which one data (DATA1) is stored within the FIFO is maintained.
Next, when second data DATA2 is input from terminal D with a pulse signal input 12-6 (write clock) at “L” level from CI terminal, DATA2 is transferred to the pipeline register in the subsequent stage, in a manner similar to DATA1. Here, however, DATA 1 has been stored in pipeline register 113 in the last stage, the “L” level signal is output from an ro terminal of a C element 116 in the last stage, and further data transfer is prohibited. Therefore, a state is maintained, in which input DATA2 is stored in the pipeline register in the (n−1)th stage, which is a stage last but one.
Similarly, while the input from RI terminal is held at “H” level, the data is successively input. When nth data DATAn is input from terminal D with a write clock 12-8 from CI terminal, DATAn is stored in a pipeline register 111 in the first stage. On the other hand, since DATA(n−1) has been stored in pipeline register 112 in the second stage (that is, the “L” level signal indicating data transfer prohibition is output from ro terminal of C element 115 in the second stage), further data transfer is not performed. Similarly, since the data has been stored in the pipeline register 111 in the first stage, further input data is not accepted. In other words, the “L” level signal indicating data transfer prohibition is output from ro terminal of C element 114 in the first stage as well as from RO terminal connected to that ro terminal. This state is referred to as a “FIFO full state.”
Next, a procedure for reading n data from the FIFO full state will be described. When a pulse signal input 12-10 (read clock) at “L” level from RI terminal is input, a C element 116 in the last stage outputs an “H” level signal 12-11 indicating termination of the data transfer operation for DATA1 from co terminal, and the “H” level signal permitting data transfer is output from ro terminal to the C element in the preceding stage. The C element in the (n−1)th stage receives the “H” level signal indicating data transfer permission from ri terminal, and transfers DATA2 to pipeline register 113 in the nth stage. Then, a read data ready state (12-13) is established.
Similarly, data from DATA3 to DATAn are transferred on one-by-one basis to the pipeline registers in the subsequent stages. As a result, pipeline register 111 in the first stage attains the empty state, and the “H” level signal (12-12) indicating that there is an empty space available in the FIFO is output from RO terminal.
Further, by inputting (n−1) read clocks from RI terminal, data from DATA2 to DATAn can be read (12-14). Here, when nth data DATAn is read, CO terminal outputs the “H” level signal. At this time point, however, the FIFO attains a completely empty state. Therefore, “H” continues to be output from CO terminal (12-15).
Thus, the circuit in FIG. 16 can easily be inserted between two external devices into which the write clock on the one hand and the read clock on the other hand are independently input in an asynchronous manner. This is because CO terminal serves as an empty flag confirming that the FIFO is in an empty state, while RO terminal serves as a full flag confirming that the FIFO is in a full state.
A role of the self-synchronous FIFO device is to smoothly transferring data between systems operating with two different clocks. The self-synchronous FIFO device introduced in conjunction with the conventional art sufficiently attains this role, because it can perform read/write to/from the FIFO independently.
Here, consider an example in which the conventional self-synchronous FIFO device is used as an interface between an asynchronous data driven information processor and a general-purpose system. In such a case, it would be more efficient, if a self-synchronous FIFO device 41 can store data of large capacity when self-synchronous FIFO device 41 performs DMA transfer of the data from an asynchronous data driven information processor 30 as shown in FIG. 18, for example, via a bus to a memory 42 by using a DMA controller 43. In order for the self-synchronous FIFO device according to the conventional art to store the data of large capacity, the data transmission paths are connected in series for storing a maximum count of data, which will lead to a larger circuit size. In addition, delay in signal propagation of the empty flag (CO terminal shown in FIG. 16)/full flag (RO terminal shown in FIG. 16) controlling a data empty state/full state within the FIFO will be more significant, and an idle time in the overall system will increase.
For example, consider an example in which the self-synchronous FIFO memory device according to the conventional art is adopted as self-synchronous FIFO memory device 41 in the system shown in FIG. 18. FIG. 18 shows an example in which self-synchronous FIFO memory device 41 is used to interface asynchronous data driven information processor 30 with a bus of CPU. In this system, the data processed in asynchronous data driven information processor 30 is accumulated in self-synchronous FIFO memory device 41. When the FIFO attains a data full state, the accumulated data is collectively subjected to DMA transfer by DMA controller 43 from self-synchronous FIFO memory device 41 to memory 42. An input controller 31 determines to which nPE the data input from the bus to asynchronous data driven information processor 30 is to be transferred. A router 32 transfers the data to a destination nPE that has been determined.
A data processing unit is represented by nPE1, nPE2, . . . , nPEn. Transferred data is processed at nPE, and transferred to an output controller 33 via router 32. Output controller 33 determines whether to transfer the data again to nPE via input controller 31 or to output the data to self-synchronous FIFO memory device 41. Self-synchronous FIFO memory device 41 accumulates the data input from asynchronous data driven information processor 30. When self-synchronous FIFO memory device 41 attains the data full state (the RO terminal shown in FIG. 16 is set to “L” level), the read clocks are collectively input from DMA controller 43 to self-synchronous FIFO memory device 41 (the “L” pulse signals are collectively input from the RI terminal shown in FIG. 16). Thus, DMA transfer is performed.
On the other hand, from an instant when the FIFO attains the full state (the RO terminal shown in FIG. 16 is set to “L” level) until the time point when the first data is read (the “L” level pulse signal is input from the RI terminal shown in FIG. 16) and a write prohibition state is reset (the RO terminal shown in FIG. 16 rises to “H” level), data write (data transfer from the output controller to self-synchronous FIFO memory device 41) cannot be carried out, even if it is desired. Since a time period from when the read clock (the “L” level pulse signal from the RI terminal) is input until when the RO terminal rises to “H” level is long (that is, propagation delay of the RO terminal is large), the write prohibition time will be extended, and a time period regarded as waste in the system is produced.
In order to reduce the idle time in the system, it is desirable to allow the FIFO device to output the full flag indicating a logically full state separately, so that burst read, that is, reading data collectively, can be carried out before the FIFO attains a completely, physically full state (here, a “physically full state” represents a state in which the data of the maximum count that the FIFO can store has been stored, while a “logically full state” represents a state in which the FIFO has stored the data of the count that a user externally designated to the FIFO). In doing so, the full flag can be output while writing is not prohibited, and data write/read to/from the FIFO can be carried out in parallel. Thus, the idle time of the system can be reduced.
As another example, consider an example in which the self-synchronous FIFO memory device according to the conventional art is adopted as the self-synchronous FIFO memory device in the system shown in FIG. 19. FIG. 19 shows an example in which a self-synchronous FIFO memory device 54 aiming at efficient data transfer is used to connect a media processor 50 consisting of a CPU 51, a memory 52, and an input/output interface 53 with a PCI bus. In this system, the data processed in CPU 51 and stored in memory 52 is subjected to burst write into self-synchronous FIFO memory device 54. When the FIFO attains the data full state, the accumulated data is subjected to burst read collectively from self-synchronous FIFO memory device 54 to a memory 56 by a DMA controller 57.
The data input from the PCI bus via input/output interface 53 to media processor 50 is processed by CPU 51, and a process result is stored in memory 52. When the empty state (the CO terminal shown in FIG. 16 is set to “H” level) in which no data is stored in self-synchronous FIFO memory device 54 is attained, the data stored in memory 52 by CPU 51 is subjected to burst transfer, and written in the FIFO by CPU 51 (the CO terminal shown in FIG. 16 is set to “L”). As a result of several times of burst write, the FIFO attains the data full state (the RO terminal shown in FIG. 16 is set to “L” level). DMA controller 57 receives this, and burst read from the FIFO to memory 56 is started (the RO terminal shown in FIG. 16 is set to “H” level).
When the FIFO attains the data empty state as a result of several times of burst read, burst write from memory 52 to the FIFO is performed again. In the system in which both burst write and burst read are performed with respect to the FIFO, reading cannot be performed during burst write, and writing cannot be performed during burst read. Therefore, the idle time in the system is produced.
In order to reduce the idle time in the system, the FIFO is provided with a full flag threshold value for recognizing the full state (logically full state) the user designated to the FIFO before the FIFO attains the completely full state as shown in the example of FIG. 18, as well as an empty threshold value for recognizing the empty state (logically empty state) the user designated to the FIFO before the FIFO attains the completely empty state (physically empty state in which no data is stored in the FIFO). If this is achieved, data transfer efficiency will be enhanced.
In the example of FIG. 19, an application is possible, in which two types of threshold values, that is the full flag threshold value and the empty flag threshold value, are provided to the FIFO, to perform burst write until the data count in the FIFO exceeds the full flag threshold value, and to perform burst read until the data count in the FIFO becomes smaller than the empty flag threshold value. In other words, in a state in which the data count in the FIFO is larger than the empty flag threshold value and smaller than the full flag threshold value, burst write and burst read can be carried out in parallel. Thus, efficient data transfer can be achieved, and the idle time in the system can be reduced. In addition, by customizing the full flag threshold value and the empty flag threshold value, the application can be adapted to a system having the different units for burst write and burst read respectively.
In the conventional FIFO memory device, however, there is no means for knowing an accurate count of data stored in the FIFO. Therefore, it is difficult to precisely control burst write/burst read.
FIG. 20 is a block diagram showing an asynchronous FIFO circuit disclosed in Japanese Patent Laying-Open No. 10-105375 as an analogous technique in the conventional art. The asynchronous FIFO circuit shown in FIG. 20 is an FIFO circuit inputting/outputting data in an asynchronous manner to/from the external device. In this circuit, when a prescribed count of data is written from a write control circuit 63 to a first FIFO 61, the count of the written data is stored in a second FIFO 62. Then, when the data is collectively read from first FIFO 61 by a read control circuit 64 based on information on the written data count within a counter 65 by that data count, the count of the read data is stored in second FIFO 62. Then, based on information on the read data count, the data is collectively written into first FIFO 61 by that data count from a write side.
The asynchronous FIFO circuit shown in FIG. 20 stores in second FIFO 62, only either information of the count of the data collectively written or the count of the data collectively read. Therefore, it is necessary to distinguish between a circuit for performing burst write and a circuit for performing burst read in FIFO 62, when performing burst write or burst read. In addition, burst write and burst read cannot be carried out in parallel. Further, when the FIFO memory is expanded so as to store data of a large capacity, the circuit size will be large.
FIG. 21 shows an asynchronous FIFO circuit disclosed in Japanese Patent Laying-Open No. 10-214174. This asynchronous FIFO circuit aims to obviate the need for synchronizing a write signal and a read signal in determining the full state/empty state so as to implement faster writing/reading, and aims to eliminate a possibility of misrecognizing the full state/empty state by removing decode processing.
This circuit is also an FIFO circuit inputting/outputting data in an asynchronous manner to/from the external device, and provided with the full flag/empty flag. A register file 71 receives input of the data of a plurality of bits from the outside, and stores the data via a write control signal. In addition, register file 71 selects the stored data of a plurality of bits via a read control signal, and outputs the data as the read data of a plurality of bits in response to an external read signal.
A write pointer 72 generates a write address signal in synchronization with an external write signal WR, and a write circuit 73 writes the data into register file 71 in response to the write address signal and the external write signal WR. A read pointer 74 generates a read address signal in synchronization with an external read signal RD, and a read circuit 75 reads the data from register file 71 in response to the read address signal.
A full/empty identification circuit 76 receives an inverted signal of external write signal WR and an inverted signal of the read signal RD, and generates and outputs a flag indicating full or empty of a shift register block contained inside.
The full flag/empty flag, however, indicates a physically full state/empty state. Therefore, the idle time in the system as shown in the examples of FIGS. 18 and 19 may be produced. In addition, in expanding so as to store the data of large capacity, the circuit size tends to be large as in the circuit shown in FIG. 16, and delay of a signal of full/empty will be significant. Accordingly, it is difficult to process in parallel asynchronous requests for read and write while assuring a normal operation. Because of these constraints, in the system requiring a FIFO memory device with a large capacity and capable of precise control of data input/output, it is difficult to insert the above-described asynchronous FIFO memory device between two devices.